use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux4:1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end mux4to1;
architecture Behavioral of mux 4:1 is
begin
process (a,b,c,d,s0,s1) is
begin
if (s0 ='0' and s1 = '0') then
y <= a;
elsif (s0 ='1' and s1 = '0') then
y <= b;
elsif (s0 ='0' and s1 = '1') then
y <= c;
else
y <= d;
end if;
end process;
end Behavioral;
