Program for components-2 input EXOR gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exor2 is
Port ( X,Y : in STD_LOGIC;
Z : out STD_LOGIC);
end exor2;
architecture Behavioral of exor2 is
begin
Z<=X xor Y;
end Behavioral;
Program for components-2 input AND gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ANDGATE2 is
Port ( P,Q : in STD_LOGIC;
R : out STD_LOGIC);
end ANDGATE2;
architecture Behavioral of ANDGATE2 is
begin
R<=P and Q;
end Behavioral;
